| Study of R S Flip Flop by NAND gates |
| |
|
SPECIFICATION : |
| |
|
Box Size : 250 x 150 x 40 mm
Input Power Supply : 230Vac, 50Hz AC Mains
Trainer consists of IC based regulated DC Power supply : 5Vdc
LEDs are provided for monitoring 0 & 1 logic levels
Toggle switches are provided for selection 0 / 1 logic level inputs
Built in Clock signal facility
|
| |
OBJECTIVE : |
|
| |
Verify truth table of Reset-Set (RS) Flip Flop logical sequencial circuit
RSFF configured by NAND gates
|
| |
|
|
| |
|
|
|
